Memory Hierarchy Analysis

Memory Hierarchy Analysis is a methodological framework within Worst-Case Execution Time Analysis that characterizes the timing effects of memory access patterns by modeling the hierarchical structure of cache and main memory to determine worst-case delays introduced by cache misses and memory contention.

426

Publications

21.8K

Citations

947

Authors

279

Institutions

Publications per year

2017–2026

38

Authors

947

  1. SA
    Sebastian Altmeyer

    University of York, United Kingdom

    9 publications · 270 citations

    9

    h-index

  2. JR
    Jan Reineke

    Saarland University, Germany

    9 publications · 665 citations

    9

    h-index

  3. RP
    Rodolfo Pellizzoni

    University of Waterloo, Canada

    7 publications · 404 citations

    7

    h-index

  4. MM
    Margaret Martonosi

    Princeton University, United States

    7 publications · 319 citations

    7

    h-index

  5. LA
    Lars Arge

    Aarhus University, Denmark

    6 publications · 241 citations

    6

    h-index

1–5 of 947

Venues

  1. IEEE Transactions on Computers

    17 publications · 914 citations

    16

    h-index

  2. ACM SIGPLAN Notices

    11 publications · 459 citations

    10

    h-index

  3. ACM SIGARCH Computer Architecture News

    10 publications · 566 citations

    10

    h-index

  4. DROPS (Schloss Dagstuhl – Leibniz Center for Informatics)

    Repository · 9 publications · 211 citations

    9

    h-index

  5. IBM Journal of Research and Development

    5 publications · 121 citations

    5

    h-index

1–5