Lot Yield Calculation

Lot Yield Calculation is a metric in semiconductor manufacturing that quantifies the proportion of functional integrated circuits produced relative to the total number of circuits fabricated within a single production lot.

5

Publications

144

Citations

13

Authors

6

Institutions

Publications per year

2017–2026

2

Authors

13

  1. SL
    Shih‐Wen Liu

    National Tsing Hua University, Taiwan

    2 publications · 35 citations

    2

    h-index

  2. FM
    Fred M. Lamb

    Virginia Tech, United States

    1 publications · 21 citations

    1

    h-index

  3. YG
    Yigal Gerchak

    University of Waterloo, Canada

    1 publications · 41 citations

    1

    h-index

  4. AJ
    Angus Jeang

    Feng Chia University, Taiwan

    1 publications · 47 citations

    1

    h-index

  5. CW
    Chien‐Wei Wu

    National Tsing Hua University, Taiwan

    1 publications · 12 citations

    1

    h-index

1–5 of 13

Venues

  1. Operations Research

    1 publications · 41 citations

    1

    h-index

  2. Quality Engineering

    1 publications · 23 citations

    1

    h-index

  3. Journal of the Operational Research Society

    OR · 1 publications · 12 citations

    1

    h-index

  4. Forest Products Journal

    FPJ · 1 publications · 21 citations

    1

    h-index

  5. Omega

    1 publications · 47 citations

    1

    h-index

1–5