Concepedia

Logic Block Packing

Logic Block Packing is a logic synthesis optimization technique that assigns and maps low-level logic elements into configurable logic blocks of a target FPGA architecture, differentiating itself by determining the most efficient grouping and placement of these elements to minimize resource usage and interconnect delay while adhering to architectural constraints.

30

Publications

1.4K

Citations

84

Authors

26

Institutions

Publications per year

2017–2026

3

Parents

Publications

30

VTR 7.0

Jason Luu, Jeffrey Goeders, Michael Wainberg et al. · ACM Transactions on Reconfigurable Technology and Systems · 2014 · 362 citations

, , +15

Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density

Alexander Marquardt, Vaughn Betz, Jonathan Rose · 1999 · 266 citations · Full text

, , +16

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Jason Luu, Jason H. Anderson, Jonathan Rose · 2011 · 83 citations

, , +17

RPack

Elaheh Bozorgzadeh, Seda Ogrenci-Memik, Majid Sarrafzadeh · 2001 · 64 citations

, , +17

ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

Eli Bozorgzadeh, Seda Öǧrenci Memik, Xi Yang et al. · Journal of Circuits Systems and Computers · 2004 · 47 citations · Full text

, , +17

1–5 of 30

Authors

84

  1. JH
    Jason H. Anderson

    University of Toronto, Canada

    7 publications · 559 citations

    7

    h-index

  2. JR
    Jonathan Rose

    University of Toronto, Canada

    5 publications · 762 citations

    5

    h-index

  3. JL
    Jason Luu

    University of Toronto, Canada

    4 publications · 491 citations

    4

    h-index

  4. MS
    Majid Sarrafzadeh

    University of California, Los Angeles, United States

    3 publications · 133 citations

    3

    h-index

  5. EB
    Eli Bozorgzadeh

    University of California, Irvine, United States

    2 publications · 69 citations

    2

    h-index

1–5 of 84

Institutions

26

  1. University of Toronto

    Toronto, Canada

    9 h-index

    28 publications

    4.6K citations

  2. Xilinx (United States)

    San Jose, United States

    4 h-index

    8 publications

    184 citations

  3. Northwestern University

    Evanston, United States

    3 h-index

    3 publications

    133 citations

  4. University of British Columbia

    Vancouver, Canada

    3 h-index

    6 publications

    481 citations

  5. University of California, Los Angeles

    Los Angeles, United States

    2 h-index

    2 publications

    111 citations

  6. Hitachi (Japan)

    Tokyo, Japan

    2 h-index

    14 publications

    420 citations

  7. National Taiwan University

    Taipei, Taiwan

    2 h-index

    6 publications

    147 citations

  8. Imperial College London

    London, United Kingdom

    2 h-index

    2 publications

    47 citations

1–8 of 26

Venues

  1. 2

    h-index

  2. Design Automation Conference

    Conference · 2 publications · 60 citations

    2

    h-index

  3. 2

    h-index

  4. 2

    h-index

  5. International Conference on Computer Aided Design

    Conference · 1 publications · 27 citations

    1

    h-index

1–5