Layout Rule Checking

Layout Rule Checking is a formal verification methodology in electronic design automation that systematically ensures a physical layout conforms to a foundry-specified set of geometric and connectivity constraints to guarantee manufacturability and electrical correctness.

76

Publications

2.4K

Citations

224

Authors

71

Institutions

Publications per year

2017–2026

7

Authors

224

  1. JK
    John K. Ousterhout

    University of California, Berkeley, United States

    10 publications · 594 citations

    10

    h-index

  2. GT
    G. Taylor

    University of California, Berkeley, United States

    6 publications · 505 citations

    6

    h-index

  3. WS
    Walter S. Scott

    University of California, Berkeley, United States

    5 publications · 380 citations

    5

    h-index

  4. GT
    Gordon T. Hamachi

    University of California, Berkeley, United States

    4 publications · 431 citations

    4

    h-index

  5. RN
    Robert N. Mayo

    University of California, Berkeley, United States

    4 publications · 431 citations

    4

    h-index

1–5 of 224

Venues

  1. Design Automation Conference

    Conference · 11 publications · 429 citations

    11

    h-index

  2. 21st Design Automation Conference Proceedings

    Conference · 5 publications · 226 citations

    5

    h-index

  3. 5

    h-index

  4. 5

    h-index

  5. 19th Design Automation Conference

    Conference · 3 publications · 43 citations

    3

    h-index

1–5