Layout Rule Checking
Layout Rule Checking is a formal verification methodology in electronic design automation that systematically ensures a physical layout conforms to a foundry-specified set of geometric and connectivity constraints to guarantee manufacturability and electrical correctness.
76
Publications
2.4K
Citations
224
Authors
71
Institutions
Publications per year
2017–2026
7
Parents
76
Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang et al. · 2018 · 208 citations
John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo et al. · Design Automation Conference · 1984 · 181 citations
John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo et al. · 21st Design Automation Conference Proceedings · 1984 · 145 citations
John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo et al. · IEEE Design & Test of Computers · 1985 · 95 citations
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University of California, Berkeley
Berkeley, United States
9 h-index
26 publications
2.4K citations
IBM (United States)
Armonk, United States
7 h-index
20 publications
250 citations
Intel (United States)
Santa Clara, United States
4 h-index
4 publications
75 citations
Siemens (Hungary)
Budapest, Hungary
3 h-index
8 publications
214 citations
Mentor Technologies
Tulsa, United States
3 h-index
6 publications
185 citations
Stanford University
Stanford, United States
3 h-index
5 publications
164 citations
Imec the Netherlands
Eindhoven, Netherlands
2 h-index
6 publications
92 citations
Digital Wave (United States)
Centennial, United States
2 h-index
2 publications
40 citations
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Conference · 11 publications · 429 citations
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Conference · 5 publications · 226 citations
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5 publications · 68 citations
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5 publications · 119 citations
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Conference · 3 publications · 43 citations
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