Latency-aware Partitioning

Latency-Aware Partitioning is a hardware-software partitioning methodology that specifically incorporates latency constraints and optimization objectives to determine the optimal allocation of system functions between hardware and software components based on timing criticality.

Publications

920

Citations

Authors

Institutions

Publications per year

2017–2026

Parents

Hardware-software Partitioning

Publications

An Effective Approach to Controller Placement in Software Defined Wide Area Networks

Guodong Wang, Yanxiao Zhao, Jun Huang et al. · IEEE Transactions on Network and Service Management · 2017 · 173 citations

Computing, Computer Science, Computer Systems +16

CLITE: Efficient and QoS-Aware Co-Location of Multiple Latency-Critical Jobs for Warehouse Scale Computers

Tirthak Patel, Devesh Tiwari · 2020 · 142 citations

Computing, Computer Science, Computer Systems +17

Partitioning of functional models of synchronous digital systems

Rohini Gupta, Giovanni De Micheli · 2002 · 99 citations

Engineering, Computer Engineering, Computer Science +15

Traffic Partition in WDM/SONET Rings to Minimize SONET ADMs

Gruiă Cälinescu, Peng‐Jun Wan · Journal of Combinatorial Optimization · 2002 · 44 citations

Computing, Computer Engineering, Computer Science +13

A new approach for FPGA-based real-time simulation of power electronic system with no simulation latency in subsystem partitioning

Chen Liu, Rui Ma, Hao Bai et al. · International Journal of Electrical Power & Energy Systems · 2018 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 26

Authors

EG
Enric Gibert
Universitat Politècnica de Catalunya, Spain
2 publications · 34 citations
2
h-index
AG
Antonio González
Universitat Politècnica de Catalunya, Spain
2 publications · 34 citations
2
h-index
RV
Ranga Vemuri
University of Cincinnati, United States
2 publications · 35 citations
2
h-index
AN
Andrew Nelson
Los Alamos National Laboratory, United States
1 publications · 11 citations
1
h-index
RM
Rui Ma
Northwestern Polytechnical University, China
1 publications · 44 citations
1
h-index

1–5 of 94

Institutions

1–8 of 47

Venues

Parallel Computing
1 publications · 12 citations
1
h-index
arXiv (Cornell University)
Repository · 1 publications · 19 citations
1
h-index
ACM Transactions on Multimedia Computing Communications and Applications
TOMCCAP · 1 publications · 31 citations
1
h-index
IEEE Transactions on Circuits and Systems I Regular Papers
1 publications · 20 citations
1
h-index
Microprocessors and Microsystems
MICPRO · 1 publications · 11 citations
1
h-index

1–5