Concepedia

Instruction Window

Instruction Window is a processor architecture construct that belongs to the category of execution management mechanisms, specifically defined as the set of instructions currently eligible for out-of-order execution and resident in the reorder buffer, distinguished by its role in tracking speculative state and enabling dynamic scheduling in pipelined processors.

98

Publications

8.3K

Citations

193

Authors

66

Institutions

Publications per year

2017–2026

3

Parents

Publications

98

Complexity-effective superscalar processors

Subbarao Palacharla, Norman P. Jouppi, James E. Smith · 1997 · 839 citations

, , +17

Runahead execution: an alternative to very large instruction windows for out-of-order processors

Onur Mutlu, Jared Stark, Chris Wilkerson et al. · 2003 · 440 citations

, , +15

Multiple-banked register file architectures

José-Lorenzo Cruz, Antonio González, Mateo Valero et al. · 2000 · 423 citations · Full text

, , +15

An Evaluation of High-Level Mechanistic Core Models

Trevor E. Carlson, Wim Heirman, Stijn Eyerman et al. · ACM Transactions on Architecture and Code Optimization · 2014 · 311 citations · Full text

, , +17

Memory dependence prediction using store sets

George Chrysos, Joel Emer · 1998 · 291 citations

, , +17

1–5 of 98

Authors

193

  1. HA
    Haitham Akkary

    Intel (United States), United States

    8 publications · 1.1K citations

    8

    h-index

  2. MV
    Mateo Valero

    Universitat Politècnica de Catalunya, Spain

    7 publications · 709 citations

    7

    h-index

  3. JE
    James E. Smith

    University of Wisconsin–Madison, United States

    7 publications · 1.5K citations

    7

    h-index

  4. ST
    Srikanth T. Srinivasan

    Intel (United States), United States

    6 publications · 684 citations

    6

    h-index

  5. RR
    Ravi Rajwar

    Intel (United States), United States

    6 publications · 684 citations

    6

    h-index

1–5 of 193

Institutions

66

  1. Intel (United States)

    Santa Clara, United States

    15 h-index

    34 publications

    4K citations

  2. The University of Texas at Austin

    Austin, United States

    11 h-index

    44 publications

    4.3K citations

  3. University of Wisconsin–Madison

    Madison, United States

    10 h-index

    19 publications

    4.4K citations

  4. Universitat Politècnica de Catalunya

    Barcelona, Spain

    8 h-index

    23 publications

    2.1K citations

  5. University of California San Diego

    San Diego, United States

    5 h-index

    12 publications

    950 citations

  6. University of Michigan

    Ann Arbor, United States

    5 h-index

    13 publications

    934 citations

  7. Institut national de recherche en sciences et technologies du numérique

    Le Chesnay-Rocquencourt, France

    5 h-index

    7 publications

    380 citations

  8. University of Maryland, College Park

    College Park, United States

    5 h-index

    6 publications

    156 citations

1–8 of 66

Venues

  1. ACM SIGARCH Computer Architecture News

    10 publications · 1.1K citations

    10

    h-index

  2. IEEE Micro

    4 publications · 196 citations

    4

    h-index

  3. IEEE Transactions on Computers

    4 publications · 200 citations

    4

    h-index

  4. ACM Transactions on Architecture and Code Optimization

    TACO · 3 publications · 348 citations

    3

    h-index

  5. IEEE Journal of Solid-State Circuits

    1 publications · 13 citations

    1

    h-index

1–5