Instruction Issue Logic

Instruction Issue Logic is a hardware control mechanism in GPU architecture that determines the scheduling and dispatch of instructions to execution units, differentiated by its role in managing instruction-level parallelism through dependency checking, resource availability, and warp schedulers' coordination.

37

Publications

2.3K

Citations

81

Authors

28

Institutions

Publications per year

2017–2026

0

Authors

81

  1. AG
    Antonio González

    Universitat Politècnica de Catalunya, Spain

    5 publications · 581 citations

    5

    h-index

  2. RL
    Richard L. Harris

    Baylor College of Medicine, United States

    3 publications · 79 citations

    3

    h-index

  3. DF
    Daniele Folegnani

    Universitat Politècnica de Catalunya, Spain

    2 publications · 303 citations

    3

    h-index

  4. RH
    R. Horst

    Tandem Diabetes Care (United States), United States

    3 publications · 79 citations

    3

    h-index

  5. GS
    Gurindar S. Sohi

    University of Wisconsin–Madison, United States

    3 publications · 398 citations

    3

    h-index

1–5 of 81

Venues

  1. ACM SIGARCH Computer Architecture News

    5 publications · 416 citations

    5

    h-index

  2. IEEE Transactions on Computers

    2 publications · 308 citations

    2

    h-index

  3. IEEE Journal of Solid-State Circuits

    1 publications · 87 citations

    1

    h-index

  4. IEEE Computer Architecture Letters

    1 publications · 13 citations

    1

    h-index

  5. International Journal of Educational Development

    IJED · 1 publications · 132 citations

    1

    h-index

1–5