Inrush Current Mitigation

Inrush Current Mitigation is a power management technique that belongs to the class of circuit-level optimization methods, specifically designed to suppress the transient surge of current during the power-up phase of power-gated blocks by controlled sequencing of power switches or staggered activation of sleep transistors.

336

Publications

11.8K

Citations

990

Authors

354

Institutions

Publications per year

2017–2026

95

Authors

990

  1. SJ
    Saeed Jazebi

    New York University, United States

    5 publications · 134 citations

    5

    h-index

  2. BK
    Byung‐il Kwon

    Hanyang University, South Korea

    5 publications · 78 citations

    5

    h-index

  3. YG
    Yingsan Geng

    Xi'an Jiaotong University, China

    5 publications · 106 citations

    5

    h-index

  4. KF
    K. Fröhlich

    École Polytechnique Fédérale de Lausanne, Switzerland

    4 publications · 756 citations

    4

    h-index

  5. AM
    Adel M. Sharaf

    University of New Brunswick, Canada

    4 publications · 56 citations

    4

    h-index

1–5 of 990

Venues

  1. IEEE Transactions on Power Delivery

    39 publications · 2.5K citations

    27

    h-index

  2. IEEE Transactions on Power Electronics

    17 publications · 1.4K citations

    16

    h-index

  3. IEEE Transactions on Industry Applications

    18 publications · 622 citations

    15

    h-index

  4. Electric Power Systems Research

    14 publications · 476 citations

    14

    h-index

  5. 12

    h-index

1–5