Inrush Current Mitigation
Inrush Current Mitigation is a power management technique that belongs to the class of circuit-level optimization methods, specifically designed to suppress the transient surge of current during the power-up phase of power-gated blocks by controlled sequencing of power switches or staggered activation of sleep transistors.
336
Publications
11.8K
Citations
990
Authors
354
Institutions
Publications per year
2017–2026
95
Parents
336
1–5 of 336
990
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354
National Cheng Kung University
Tainan City, Taiwan
8 h-index
25 publications
1.1K citations

Xi'an Jiaotong University
Xi'an, China
8 h-index
33 publications
640 citations
National Tsing Hua University
Hsinchu, Taiwan
8 h-index
17 publications
538 citations
University of Tabriz
Tabriz, Iran
7 h-index
20 publications
703 citations

Huazhong University of Science and Technology
Wuhan, China
7 h-index
34 publications
693 citations

North China Electric Power University
Beijing, China
6 h-index
22 publications
566 citations
Amirkabir University of Technology
Tehran, Iran
6 h-index
10 publications
300 citations

Hanyang University
Seoul, South Korea
5 h-index
11 publications
164 citations
1–8 of 354
39 publications · 2.5K citations
27
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17 publications · 1.4K citations
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18 publications · 622 citations
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14 publications · 476 citations
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13 publications · 388 citations
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