Hold Delay

Hold Delay is a timing constraint model in digital circuit design that specifies the minimum required duration for which a signal must remain stable at the input of a sequential element after a clock edge, ensuring correct data capture by preventing premature data transitions.

30

Publications

709

Citations

111

Authors

50

Institutions

Publications per year

2017–2026

8

Authors

111

  1. YZ
    Yushi Zhou

    Toronto Metropolitan University, Canada

    2 publications · 32 citations

    2

    h-index

  2. KC
    K.W. Current

    University of California, Davis, United States

    2 publications · 26 citations

    2

    h-index

  3. JA
    Janet A.W. Elliott

    University of Alberta, Canada

    2 publications · 57 citations

    2

    h-index

  4. PP
    Parth Parekh

    Toronto Metropolitan University, Canada

    2 publications · 32 citations

    2

    h-index

  5. LM
    L.E. McGann

    University of Alberta, Canada

    2 publications · 57 citations

    2

    h-index

1–5 of 111

Venues

  1. Cryobiology

    3 publications · 74 citations

    3

    h-index

  2. Electronics Letters

    1 publications · 12 citations

    1

    h-index

  3. IEEE Transactions on Industrial Electronics

    1 publications · 68 citations

    1

    h-index

  4. Poultry Science

    1 publications · 15 citations

    1

    h-index

  5. 1

    h-index

1–5