Hierarchical Rule Checking

Hierarchical Rule Checking is a formal verification methodology within Design Rule Checking that systematically validates integrated circuit layouts by propagating rule checks across multiple levels of a design hierarchy, preserving structural abstraction to enhance computational efficiency and scalability.

20

Publications

736

Citations

31

Authors

14

Institutions

Publications per year

2017–2026

2

Authors

31

  1. JK
    John K. Ousterhout

    University of California, Berkeley, United States

    4 publications · 119 citations

    4

    h-index

  2. GK
    Gershon Kedem

    Duke University, United States

    3 publications · 153 citations

    3

    h-index

  3. AR
    Andrew R. Pleszkun

    University of Colorado Boulder, United States

    2 publications · 27 citations

    2

    h-index

  4. MH
    Michael H. Arnold

    University of California, Berkeley, United States

    2 publications · 45 citations

    2

    h-index

  5. GE
    George E. Bier

    University of Wisconsin–Madison, United States

    2 publications · 27 citations

    2

    h-index

1–5 of 31

Venues

  1. Design Automation Conference

    Conference · 4 publications · 97 citations

    4

    h-index

  2. 19th Design Automation Conference

    Conference · 2 publications · 56 citations

    2

    h-index

  3. 20th Design Automation Conference Proceedings

    Conference · 1 publications · 12 citations

    1

    h-index

  4. 1

    h-index

  5. IEEE Transactions on Consumer Electronics

    1 publications · 43 citations

    1

    h-index

1–5