Hierarchical Rule Checking
Hierarchical Rule Checking is a formal verification methodology within Design Rule Checking that systematically validates integrated circuit layouts by propagating rule checks across multiple levels of a design hierarchy, preserving structural abstraction to enhance computational efficiency and scalability.
20
Publications
736
Citations
31
Authors
14
Institutions
Publications per year
2017–2026
2
Parents
20
1–5 of 20
31
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14
University of California, Berkeley
Berkeley, United States
4 h-index
7 publications
209 citations
General Electric (United States)
Boston, United States
2 h-index
2 publications
24 citations

University of Rochester
Rochester, United States
2 h-index
2 publications
137 citations
University of Illinois Chicago
Chicago, United States
1 h-index
2 publications
48 citations
Chalmers University of Technology
Gothenburg, Sweden
1 h-index
2 publications
34 citations
California Institute of Technology
Pasadena, United States
1 h-index
2 publications
22 citations

Sri Venkateswara University
Tirumala - Tirupati, India
1 h-index
2 publications
46 citations
National Institute of Standards and Technology
Gaithersburg, United States
1 h-index
1 publications
82 citations
1–8 of 14
Conference · 4 publications · 97 citations
4
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Conference · 2 publications · 56 citations
2
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Conference · 1 publications · 12 citations
1
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Conference · 1 publications · 16 citations
1
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1 publications · 43 citations
1
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1–5