Hierarchical Identifier

A Hierarchical Identifier is a formal syntactic construct in Verilog that uniquely specifies a signal, module, or instance within a nested design hierarchy by concatenating ancestor module names with the target identifier using dot notation.

5

Publications

183

Citations

24

Authors

9

Institutions

Publications per year

2017–2026

2

Authors

24

  1. RJ
    Raj Jain

    Washington University in St. Louis, United States

    2 publications · 118 citations

    2

    h-index

  2. MB
    Mic Bowman

    Intel (United States), United States

    2 publications · 118 citations

    2

    h-index

  3. JP
    Jianli Pan

    University of Missouri–St. Louis, United States

    2 publications · 118 citations

    2

    h-index

  4. SP
    Subharthi Paul

    Washington University in St. Louis, United States

    1 publications · 77 citations

    1

    h-index

  5. TQ
    Tong Qiao

    Hangzhou Dianzi University, China

    1 publications · 19 citations

    1

    h-index

1–5 of 24

Venues

  1. IEEE Wireless Communications

    1 publications · 18 citations

    1

    h-index

  2. Sensors

    1 publications · 19 citations

    1

    h-index

1–3