Hardware Tessellation

Hardware Tessellation is a graphics processing technique that belongs to the class of geometric subdivision methods, distinguished by its implementation in dedicated GPU hardware to dynamically refine coarse polygon meshes into finer geometric detail during rendering.

25

Publications

622

Citations

57

Authors

26

Institutions

Publications per year

2017–2026

3

Authors

57

  1. CL
    Charles Loop

    Microsoft (United States), United States

    7 publications · 227 citations

    7

    h-index

  2. MN
    Matthias Nießner

    Technical University of Munich, Germany

    5 publications · 121 citations

    5

    h-index

  3. MS
    Marc Stamminger

    Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

    4 publications · 74 citations

    4

    h-index

  4. BK
    Benjamin Keinert

    Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

    3 publications · 64 citations

    3

    h-index

  5. HS
    Henry Schäfer

    Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

    3 publications · 64 citations

    3

    h-index

1–5 of 57

Venues

  1. Computer Graphics Forum

    4 publications · 73 citations

    4

    h-index

  2. ACM Transactions on Graphics

    TOG · 3 publications · 149 citations

    3

    h-index

  3. IEEE Transactions on Visualization and Computer Graphics

    TVCG · 1 publications · 10 citations

    1

    h-index

  4. IEEE Transactions on Computers

    1 publications · 13 citations

    1

    h-index

  5. 1

    h-index

1–5