Concepedia

Global Interconnect Optimization

Global Interconnect Optimization is a systematic design methodology within integrated circuit physical synthesis that addresses the holistic improvement of signal routing networks across an entire chip to minimize delay, power consumption, and area while maintaining signal integrity.

52

Publications

3.3K

Citations

92

Authors

40

Institutions

Publications per year

2017–2026

1

Parents

Publications

52

Force-directed scheduling for the behavioral synthesis of ASICs

Pierre Paulin, J.P. Knight · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1989 · 1.1K citations

, , +16

TimberWolf3.2: A New Standard Cell Placement and Global Routing Package

Carl Sechen, Alberto Sangiovanni‐Vincentelli · Design Automation Conference · 1986 · 187 citations

, , +16

A Global Interconnect Optimization Scheme for Nanometer Scale VLSI With Implications for Latency, Bandwidth, and Power Dissipation

Man Mui, Kaustav Banerjee, A. Mehrotra · IEEE Transactions on Electron Devices · 2004 · 111 citations

, , +17

A survey on multi-net global routing for integrated circuits

Jiang Hu, Sachin S. Sapatnekar · Integration · 2001 · 107 citations

, , +14

Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation

X.-C. Li, J.-F. Mao, Hui‐Fen Huang et al. · IEEE Transactions on Electron Devices · 2005 · 100 citations

, , +17

1–5 of 52

Authors

92

  1. JC
    Jason Cong

    University of California, Los Angeles, United States

    5 publications · 203 citations

    5

    h-index

  2. JM
    J.D. Meindl

    Georgia Institute of Technology, United States

    5 publications · 161 citations

    5

    h-index

  3. LH
    Lei He

    University of California, Los Angeles, United States

    4 publications · 133 citations

    4

    h-index

  4. EK
    E.S. Kuh

    University of California, Berkeley, United States

    4 publications · 188 citations

    4

    h-index

  5. AB
    Andrew B. Kahng

    University of California San Diego, United States

    3 publications · 116 citations

    3

    h-index

1–5 of 92

Institutions

40

  1. University of California, Los Angeles

    Los Angeles, United States

    10 h-index

    18 publications

    609 citations

  2. Georgia Institute of Technology

    Atlanta, United States

    8 h-index

    19 publications

    526 citations

  3. University of California, Berkeley

    Berkeley, United States

    6 h-index

    14 publications

    930 citations

  4. University of Michigan

    Ann Arbor, United States

    4 h-index

    10 publications

    260 citations

  5. Silicon Labs (United States)

    Austin, United States

    4 h-index

    8 publications

    346 citations

  6. IBM Research - Thomas J. Watson Research Center

    Yorktown Heights, United States

    3 h-index

    3 publications

    69 citations

  7. IBM (United States)

    Armonk, United States

    2 h-index

    2 publications

    48 citations

  8. University of Tehran

    Tehran, Iran

    2 h-index

    4 publications

    44 citations

1–8 of 40

Venues

  1. 7

    h-index

  2. IEEE Transactions on Electron Devices

    4 publications · 274 citations

    4

    h-index

  3. 3

    h-index

  4. IEEE Spectrum

    2 publications · 65 citations

    2

    h-index

  5. 23rd ACM/IEEE Design Automation Conference

    Conference · 1 publications · 99 citations

    1

    h-index

1–5