Flip-flop Integration

Flip-Flop Integration is a methodological construct within the architecture of Field-Programmable Gate Arrays that embeds flip-flops directly into configurable logic blocks to enhance timing performance and resource utilization by enabling efficient synchronization within programmable logic fabrics.

44

Publications

1.7K

Citations

166

Authors

52

Institutions

Publications per year

2017–2026

7

Authors

166

  1. PM
    Pavlos Maniotis

    Aristotle University of Thessaloniki, Greece

    3 publications · 67 citations

    3

    h-index

  2. KM
    Koichi Murata

    NTT (Japan), Japan

    3 publications · 86 citations

    3

    h-index

  3. NP
    Nikos Pleros

    Aristotle University of Thessaloniki, Greece

    3 publications · 67 citations

    3

    h-index

  4. CV
    Christos Vagionas

    Aristotle University of Thessaloniki, Greece

    3 publications · 67 citations

    3

    h-index

  5. GM
    George Mourgias-Alexandris

    Aristotle University of Thessaloniki, Greece

    2 publications · 48 citations

    2

    h-index

1–5 of 166

Venues

  1. Electronics Letters

    4 publications · 159 citations

    4

    h-index

  2. 2

    h-index

  3. IEEE Photonics Technology Letters

    IPTEL · 2 publications · 36 citations

    2

    h-index

  4. 2

    h-index

  5. 1

    h-index

1–5