Field-Programmable Gate Array Reconfiguration is a reconfiguration process that enables dynamic modification of the hardware functionality of a Field-Programmable Gate Array during run time by altering its configuration bitstream while preserving operational continuity in embedded systems.
191
Publications
8.2K
Citations
553
Authors
197
Institutions
Publications per year
2017–2026
20
Variants
Fpga Reconfiguration
Parents
Publications
191
JHDL-an HDL for reconfigurable systems
Peter Bellows, Brad Hutchings · 2002 · 249 citations
A reconfigurable arithmetic array for multimedia applications
Alan Marshall, Tony Stansfield, Igor Kostarnov et al. · 1999 · 168 citations · Full text
1–5 of 191
Authors
553
- JB
7
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- MH
6
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- BH
5
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- JW
4
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- DK
4
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1–5 of 553
Institutions
197
Nanyang Technological University
Singapore, Singapore
6 h-index
14 publications
563 citations
University of California, Berkeley
Berkeley, United States
6 h-index
10 publications
854 citations
Brigham Young University
Provo, United States
5 h-index
8 publications
979 citations
Jet Propulsion Laboratory
Pasadena, United States
5 h-index
23 publications
946 citations
University of Toronto
Toronto, Canada
5 h-index
10 publications
528 citations
University of California, Los Angeles
Los Angeles, United States
5 h-index
10 publications
355 citations
Ruhr University Bochum
Bochum, Germany
4 h-index
11 publications
220 citations
California Institute of Technology
Pasadena, United States
4 h-index
10 publications
535 citations
1–8 of 197
Venues
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
8 publications · 542 citations
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- Proceedings - ACM IEEE Design Automation Conference
3 publications · 164 citations
3
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- Sensors
3 publications · 132 citations
3
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- IEEE Transactions on Computers
3 publications · 244 citations
3
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- IEEE Transactions on Circuits & Systems II Express Briefs
3 publications · 115 citations
3
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