Field-programmable Gate Array Prototyping
Field-Programmable Gate Array Prototyping is a hardware design methodology that employs reconfigurable field-programmable gate arrays to emulate and validate the functionality of application-specific integrated circuits prior to fabrication, enabling rapid iteration and verification of digital system architectures.
142
Publications
6.7K
Citations
523
Authors
186
Institutions
Publications per year
2017–2026
29
142
Kevin E. Murray, Oleg Petelin, Sheng Zhong et al. · ACM Transactions on Reconfigurable Technology and Systems · 2020 · 293 citations
1–5 of 142
523
3
h-index
3
h-index
3
h-index
3
h-index
3
h-index
1–5 of 523
186

University of Toronto
Toronto, Canada
6 h-index
21 publications
3.7K citations

Centre National de la Recherche Scientifique
Paris, France
5 h-index
14 publications
366 citations

Indian Institute of Technology Hyderabad
Sangāreddi, India
4 h-index
11 publications
387 citations

Technische Universität Darmstadt
Darmstadt, Germany
4 h-index
13 publications
373 citations
Georgia Institute of Technology
Atlanta, United States
4 h-index
11 publications
722 citations

Anglia Ruskin University
Cambridge, United Kingdom
3 h-index
5 publications
164 citations

University of Zielona Góra
Zielona Góra, Poland
3 h-index
7 publications
237 citations
Intel (United States)
Santa Clara, United States
2 h-index
2 publications
58 citations
1–8 of 186
5 publications · 183 citations
5
h-index
4 publications · 541 citations
4
h-index
4 publications · 94 citations
4
h-index
4 publications · 223 citations
4
h-index
3 publications · 56 citations
3
h-index
1–5