Publication | Closed Access
High-Level Synthesis for FPGAs: From Prototyping to Deployment
826
Citations
80
References
2011
Year
EngineeringHls ToolsComputer ArchitectureSystem-level DesignSystem SynthesisHigh-level SynthesisHardware ArchitectureHardware SecuritySystems EngineeringHls SolutionsHardware Description LanguageParallel ComputingCompilersAutopilot Hls ToolComputer EngineeringComputer ScienceReconfigurable ArchitectureFpga DesignSoftware DesignLogic SynthesisHardware EmulationFormal Methods
Increasing SoC complexity drives a shift beyond RTL, and recent HLS tools now offer broad language support, robust compilation, and domain‑specific features, marking a tipping point for FPGA design. The paper demonstrates the effectiveness of modern C‑to‑FPGA HLS solutions across multiple domains using AutoESL's AutoPilot and Xilinx platforms. The authors employ AutoESL's AutoPilot HLS tool with Xilinx platform‑based designs, presenting industrial case studies that compare HLS against hand‑optimized manual implementations. An experiment on a sphere decoder demonstrates that HLS reduces FPGA resource usage by 11–31% while improving design productivity versus hand‑coded designs.
Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.
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