Delay-Voltage Tradeoff is a phenomenon in subthreshold circuit design characterized by the inverse relationship between supply voltage and signal propagation delay, wherein reducing voltage increases delay due to diminished driving strength of transistors.
5
Publications
130
Citations
13
Authors
4
Institutions
Publications per year
2017–2026
1
Parents
Publications
5
Optimal voltages and sizing for low power [CMOS VLSI]
Mircea R. Stan · 1999 · 44 citations
Engineering, Computer Engineering, Electrical Engineering +17
A monitor interconnect and support subsystem for multicore processors
S. Madduri, Ramakrishna Vadlamani, Wayne Burleson et al. · 2009 · 27 citations
1–5 of 5
Authors
13
- RT
2
h-index
- RVRamakrishna Vadlamani
University of Massachusetts Amherst, United States
2 publications · 57 citations
2
h-index
- WB
2
h-index
- ASA. S. Gilmour
University at Buffalo, State University of New York, United States
1 publications · 17 citations
1
h-index
- SM
1
h-index
1–5 of 13
Institutions
4
University of Massachusetts Amherst
Amherst Center, United States
2 h-index
8 publications
228 citations
University of Virginia
Charlottesville, United States
1 h-index
1 publications
44 citations
Crawley Hospital
Crawley, United Kingdom
1 h-index
2 publications
34 citations
Dr. Hari Singh Gour University
Saugor, India
1 h-index
5 publications
60 citations
1–4 of 4
Venues
- Journal of Applied Electrochemistry
1 publications · 17 citations
1
h-index
- Scholarworks (University of Massachusetts Amherst)
Repository · 1 publications · 30 citations
1
h-index
- Analog Integrated Circuits and Signal Processing
1 publications · 12 citations
1
h-index
1–3