Combinational Equivalence Checking is a formal verification method that belongs to the class of equivalence checking techniques, distinguished by its focus on proving the functional equivalence of two combinational logic circuits without considering sequential behavior or internal state.
75
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3.4K
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127
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49
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Publications per year
2017–2026
4
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Publications
75
Using SAT for combinational equivalence checking
E. Goldberg, Mukul R. Prasad, Robert K. Brayton · 2001 · 135 citations
1–5 of 75
Authors
127
- RK
13
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8
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8
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5
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1–5 of 127
Institutions
49
University of California, Berkeley
Berkeley, United States
14 h-index
39 publications
2.3K citations
Cadence Design Systems (United States)
San Jose, United States
10 h-index
12 publications
752 citations
Lawrence Berkeley National Laboratory
Berkeley, United States
7 h-index
9 publications
572 citations
University of British Columbia
Vancouver, Canada
5 h-index
7 publications
183 citations
Synopsys (United States)
Mountain View, United States
4 h-index
9 publications
120 citations
The University of Tokyo
Tokyo, Japan
4 h-index
14 publications
354 citations
Fujitsu (Japan)
Kawasaki, Japan
3 h-index
5 publications
141 citations
Goethe University Frankfurt
Frankfurt am Main, Germany
3 h-index
5 publications
85 citations
1–8 of 49
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
5 publications · 208 citations
5
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- International Conference on Computer Aided Design
Conference · 4 publications · 366 citations
4
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- Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 3 publications · 245 citations
3
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- Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
Conference · 2 publications · 263 citations
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- Proceedings - ACM IEEE Design Automation Conference
2 publications · 45 citations
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1–5