Coherent Cache Hierarchies

Coherent Cache Hierarchies is a cache coherence protocol architecture that ensures consistent data representation across multiple processor caches in a shared-memory multiprocessor system by maintaining a unified view of memory through coordinated update and invalidation mechanisms.

16

Publications

365

Citations

51

Authors

20

Institutions

Publications per year

2017–2026

2

Authors

51

  1. JL
    John L. Hennessy

    Stanford University, United States

    2 publications · 118 citations

    2

    h-index

  2. JS
    Jaswinder Singh

    Princeton University, United States

    2 publications · 28 citations

    2

    h-index

  3. JT
    Josep Torrellas

    University of Illinois Urbana-Champaign, United States

    1 publications · 18 citations

    1

    h-index

  4. PB
    Pavan Balaji

    Argonne National Laboratory, United States

    1 publications · 20 citations

    1

    h-index

  5. GS
    Gopalakrishnan Santhanaraman

    The Ohio State University, United States

    1 publications · 20 citations

    1

    h-index

1–5 of 51

Venues

  1. IEEE Micro

    2 publications · 31 citations

    1

    h-index

  2. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 1 publications · 27 citations

    1

    h-index

  3. ACM Transactions on Computer Systems

    TOCS · 1 publications · 72 citations

    1

    h-index

  4. 1

    h-index

  5. Conference on High Performance Computing (Supercomputing)

    Conference · 1 publications · 11 citations

    1

    h-index

1–5