Coherent Cache Hierarchies
Coherent Cache Hierarchies is a cache coherence protocol architecture that ensures consistent data representation across multiple processor caches in a shared-memory multiprocessor system by maintaining a unified view of memory through coordinated update and invalidation mechanisms.
16
Publications
365
Citations
51
Authors
20
Institutions
Publications per year
2017–2026
2
16
The DASH Prototype: Implementation and Performance
Daniel Lenoski, James Laudon, Truman Joe et al. · 2005 · 46 citations
Berkin Akin, Zeshan Chishti, Alaa R. Alameldeen · 2019 · 26 citations
1–5 of 16
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20
University of Illinois Urbana-Champaign
Urbana, United States
3 h-index
5 publications
84 citations
Stanford University
Stanford, United States
3 h-index
13 publications
510 citations
Princeton University
Princeton, United States
2 h-index
3 publications
92 citations
Intel (United States)
Santa Clara, United States
2 h-index
4 publications
100 citations
Nature Inspires Creativity Engineers Lab
Nice, France
1 h-index
1 publications
20 citations
Argonne National Laboratory
Lemont, United States
1 h-index
2 publications
40 citations

Uppsala University
Uppsala, Sweden
1 h-index
2 publications
56 citations
Micron (United States)
Boise, United States
1 h-index
2 publications
40 citations
1–8 of 20
2 publications · 31 citations
1
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TPDS · 1 publications · 27 citations
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TOCS · 1 publications · 72 citations
1
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Repository · 1 publications · 10 citations
1
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Conference · 1 publications · 11 citations
1
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