Clock Power Estimation

Clock Power Estimation is a methodological framework within power estimation that specifically quantifies the dynamic and static power consumption attributable to the clock distribution network in synchronous digital circuits.

32

Publications

909

Citations

117

Authors

51

Institutions

Publications per year

2017–2026

5

Authors

117

  1. AE
    Alan E. Willner

    University of Southern California, United States

    3 publications · 139 citations

    3

    h-index

  2. MI
    M.J. Irwin

    Pennsylvania State University, United States

    3 publications · 81 citations

    3

    h-index

  3. ZP
    Zhongqi Pan

    University of Southern California, United States

    3 publications · 139 citations

    3

    h-index

  4. VG
    Vojin G. Oklobdzija

    University of California, Davis, United States

    2 publications · 95 citations

    2

    h-index

  5. YS
    Yong‐Won Song

    Korea Institute of Science and Technology, South Korea

    2 publications · 106 citations

    2

    h-index

1–5 of 117

Venues

  1. IEEE Photonics Technology Letters

    IPTEL · 2 publications · 113 citations

    2

    h-index

  2. IEEE Journal of Solid-State Circuits

    2 publications · 51 citations

    2

    h-index

  3. 1

    h-index

  4. 1

    h-index

  5. Pervasive and Mobile Computing

    1 publications · 15 citations

    1

    h-index

1–5