Clock Power Estimation
Clock Power Estimation is a methodological framework within power estimation that specifically quantifies the dynamic and static power consumption attributable to the clock distribution network in synchronous digital circuits.
32
Publications
909
Citations
117
Authors
51
Institutions
Publications per year
2017–2026
5
Parents
32
Clock-tone regeneration due to higher order PMD in NRZ systems
Zhongqi Pan, Qian Yu, Yiyuan Xie et al. · IEEE Photonics Technology Letters · 2003 · 80 citations
Power Reduction by Clock Gating Technique
Nandita Srinivasan, Navamitha S. Prakash, D. Shalakha et al. · Procedia Technology · 2015 · 38 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
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University of Southern California
Los Angeles, United States
3 h-index
15 publications
594 citations
University of California, Davis
Davis, United States
3 h-index
3 publications
127 citations

Carleton University
Ottawa, Canada
2 h-index
3 publications
135 citations

Pennsylvania State University
State College, United States
2 h-index
6 publications
198 citations
Technical University of Munich
Munich, Germany
2 h-index
7 publications
182 citations
Institute of Navigation
Manassas, United States
1 h-index
1 publications
17 citations
Engineering Systems (United States)
Omaha, United States
1 h-index
3 publications
240 citations

Concordia University
Montreal, Canada
1 h-index
3 publications
36 citations
1–8 of 51
IPTEL · 2 publications · 113 citations
2
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2 publications · 51 citations
2
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1 publications · 31 citations
1
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1 publications · 18 citations
1
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1 publications · 15 citations
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