Charge-recovery power clock generators for adiabatic logic circuits

Abstract

To get maximum energy efficiency from adiabatic logic circuits several charge-recovery power clock generators (PCGs) have been published in recent years. This paper compares and analyzes the performance and energy efficiency of various PCGs in a uniform test environment. The test benches are laid out in a standard 0.18 /spl mu/m CMOS technology and the results are mainly based on post layout simulations.