Concepedia

Circuit Equivalence Checking

Circuit Equivalence Checking is a formal verification method that belongs to the class of equivalence checking techniques, distinguished by its specific application to determining whether two digital circuit representations exhibit identical input-output behavior under a given set of equivalence criteria.

212

Publications

7.3K

Citations

379

Authors

148

Institutions

Publications per year

2017–2026

22

Parents

Publications

212

Robust Boolean reasoning for equivalence checking and functional property verification

Andreas Kuehlmann, Viresh Paruthi, F. Krohm et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2002 · 331 citations

, , +16

The EPFL Combinational Benchmark Suite

Luca Amarù, Pierre‐Emmanuel Gaillardon · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2019 · 290 citations · Full text

, , +17

Circuit-based Boolean Reasoning

Andreas Kuehlmann, Malay Ganai, Viresh Paruthi · 2001 · 154 citations

, , +15

Improvements to combinational equivalence checking

Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 130 citations

, , +16

FRAIGs: A Unifying Representation for Logic Synthesis and Verification

Alan Mishchenko, Satrajit Chatterjee, Roland Jiang et al. · 2005 · 128 citations

, , +17

1–5 of 212

Authors

379

  1. RD
    Rolf Drechsler

    University of Bremen, Germany

    10 publications · 306 citations

    10

    h-index

  2. RW
    Robert Wille

    Johannes Kepler University of Linz, Austria

    10 publications · 386 citations

    10

    h-index

  3. IL
    Igor L. Markov

    University of Michigan, United States

    8 publications · 276 citations

    8

    h-index

  4. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    8 publications · 458 citations

    8

    h-index

  5. MF
    Masahiro Fujita

    The University of Tokyo, Japan

    8 publications · 279 citations

    8

    h-index

1–5 of 379

Institutions

148

  1. University of California, Berkeley

    Berkeley, United States

    13 h-index

    29 publications

    1.4K citations

  2. Cadence Design Systems (United States)

    San Jose, United States

    12 h-index

    15 publications

    1.1K citations

  3. Fujitsu (United States)

    Sunnyvale, United States

    11 h-index

    18 publications

    708 citations

  4. University of Bremen

    Bremen, Germany

    10 h-index

    23 publications

    669 citations

  5. Lawrence Berkeley National Laboratory

    Berkeley, United States

    10 h-index

    11 publications

    1K citations

  6. Intel (United States)

    Santa Clara, United States

    9 h-index

    14 publications

    386 citations

  7. The University of Texas at Austin

    Austin, United States

    9 h-index

    19 publications

    618 citations

  8. University of Michigan

    Ann Arbor, United States

    8 h-index

    17 publications

    679 citations

1–8 of 148

Venues

  1. 18

    h-index

  2. 5

    h-index

  3. 4

    h-index

  4. Formal Methods in System Design

    3 publications · 90 citations

    3

    h-index

  5. IEEE Transactions on Computers

    3 publications · 106 citations

    3

    h-index

1–5