Capability-Based Memory Safety is a memory safety paradigm that enforces access control and prevents spatial and temporal memory errors by requiring that all memory accesses be mediated through unforgeable capabilities, which are protected references containing both address and permission information.
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477
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37
Authors
7
Institutions
Publications per year
2017–2026
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Publications
5
Jonathan Woodruff, Robert N. M. Watson, David Chisnall et al. · ACM SIGARCH Computer Architecture News · 2014 · 214 citations
The CHERI capability model: Revisiting RISC in an age of risk
Jonathan Woodruff, Robert N. M. Watson, David Chisnall et al. · 2014 · 159 citations
Brooks Davis, Robert N. M. Watson, Alexander Richardson et al. · 2019 · 57 citations · Full text
Cryptographic Capability Computing
Michael LeMay, Joydeep Rakshit, Sergej Deutsch et al. · 2021 · 27 citations · Full text
CheriRTOS: A Capability Model for Embedded Devices
Hongyan Xia, Jonathan Woodruff, Hadrien Barral et al. · 2018 · 20 citations · Full text
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Authors
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Institutions
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SRI International
Menlo Park, United States
4 h-index
9 publications
920 citations
University of Cambridge
Cambridge, United Kingdom
4 h-index
43 publications
3.8K citations
Google (United Kingdom)
London, United Kingdom
3 h-index
3 publications
430 citations
Menlo School
Atherton, United States
2 h-index
5 publications
174 citations
Intel (United States)
Santa Clara, United States
1 h-index
7 publications
189 citations
Intel (India)
Bengaluru, India
1 h-index
4 publications
108 citations
Microsoft Research (United Kingdom)
Cambridge, United Kingdom
1 h-index
1 publications
57 citations
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Venues
- ACM SIGARCH Computer Architecture News
1 publications · 214 citations
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