Cache Line Compression is a low-power cache optimization technique that reduces effective cache line size by encoding data to minimize storage and transmission overhead, thereby improving energy efficiency without compromising functional correctness.
33
Publications
1.6K
Citations
92
Authors
34
Institutions
Publications per year
2017–2026
13
Parents
Publications
33
1–5 of 33
Authors
92
- DA
6
h-index
- AM
6
h-index
- EM
6
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- AR
5
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- LB
4
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1–5 of 92
Institutions
34
University of Wisconsin–Madison
Madison, United States
6 h-index
10 publications
1.1K citations
Politecnico di Torino
Turin, Italy
6 h-index
11 publications
282 citations
University of Bologna
Bologna, Italy
4 h-index
9 publications
325 citations
Huazhong University of Science and Technology
Wuhan, China
3 h-index
18 publications
324 citations
Intel (United States)
Santa Clara, United States
3 h-index
4 publications
112 citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
2 h-index
7 publications
196 citations
University of Michigan
Ann Arbor, United States
2 h-index
4 publications
183 citations
Massachusetts Institute of Technology
Cambridge, United States
2 h-index
5 publications
112 citations
1–8 of 34
Venues
- Minds at UW (University of Wisconsin)
Repository · 1 publications · 193 citations
1
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- 2003 Design, Automation and Test in Europe Conference and Exhibition
Conference · 1 publications · 10 citations
1
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 19 citations
1
h-index
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1 publications · 13 citations
1
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- Proceedings of the VLDB Endowment
PVLDB · 1 publications · 75 citations
1
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1–5