Cache Hit Rate Optimization is an algorithmic strategy in computer architecture that enhances data access efficiency by maximizing the proportion of successful cache accesses relative to total memory requests through intelligent placement, replacement, and prefetching policies.
206
Publications
11K
Citations
580
Authors
233
Institutions
Publications per year
2017–2026
69
Parents
Publications
206
Adaptive insertion policies for high performance caching
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt et al. · 2007 · 633 citations
Daniel Vogel, Patrick Baudisch · 2007 · 471 citations
Compiler optimizations for improving data locality
Steve Carr, Kathryn S. McKinley, Chau‐Wen Tseng · 1994 · 294 citations · Full text
1–5 of 206
Authors
580
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1–5 of 580
Institutions
233
Intel (United States)
Santa Clara, United States
8 h-index
19 publications
2.7K citations
University of Massachusetts Amherst
Amherst Center, United States
7 h-index
15 publications
1.1K citations
Stanford University
Stanford, United States
6 h-index
10 publications
786 citations
Tsinghua University
Beijing, China
5 h-index
14 publications
484 citations
The University of Texas at Austin
Austin, United States
5 h-index
9 publications
2K citations
Pennsylvania State University
State College, United States
5 h-index
12 publications
525 citations
Southeast University
Nanjing, China
5 h-index
15 publications
947 citations
Intel (United Kingdom)
Swindon, United Kingdom
4 h-index
14 publications
338 citations
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Venues
- ACM SIGARCH Computer Architecture News
10 publications · 442 citations
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- IEEE Access
8 publications · 275 citations
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- IEEE Transactions on Wireless Communications
5 publications · 175 citations
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- ACM SIGMETRICS Performance Evaluation Review
PER · 4 publications · 101 citations
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- IEEE Internet of Things Journal
4 publications · 228 citations
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