Concepedia

Cache Hierarchy Coherence

Cache Hierarchy Coherence is a cache coherence protocol that ensures consistent data representation across multiple levels of a processor's memory hierarchy by maintaining temporal and structural alignment of cached copies within nested cache levels.

3

Publications

67

Citations

9

Authors

6

Institutions

Publications per year

2017–2026

0

Parents

Publications

3

1–3 of 3

Authors

9

  1. MD
    Mahdad Davari

    Universidad de Murcia, Spain

    1 publications · 28 citations

    1

    h-index

  2. CC
    Ching-Tsun Chou

    Intel (United States), United States

    1 publications · 20 citations

    1

    h-index

  3. GG
    Ganesh Gopalakrishnan

    University of Utah, United States

    1 publications · 20 citations

    1

    h-index

  4. SK
    Stefanos Kaxiras

    Uppsala University, Sweden

    1 publications · 28 citations

    1

    h-index

  5. AR
    Alberto Ros

    Universidad de Murcia, Spain

    1 publications · 28 citations

    1

    h-index

1–5 of 9

Institutions

6

  1. Intel (United States)

    Santa Clara, United States

    1 h-index

    1 publications

    20 citations

  2. Uppsala University

    Uppsala, Sweden

    1 h-index

    2 publications

    56 citations

  3. Universidad de Murcia

    Murcia, Spain

    1 h-index

    1 publications

    28 citations

  4. University of Utah

    Salt Lake City, United States

    1 h-index

    3 publications

    60 citations

  5. Georgia Institute of Technology

    Atlanta, United States

    1 h-index

    1 publications

    19 citations

  6. Michigan State University

    East Lansing, United States

    1 h-index

    1 publications

    19 citations

1–6 of 6

Venues

  1. Formal Methods in System Design

    1 publications · 20 citations

    1

    h-index

  2. Automatica

    1 publications · 19 citations

    1

    h-index

1–2