Bypass Networks
Bypass Networks is a hardware optimization mechanism in out-of-order execution processors that belongs to the class of data forwarding techniques, distinguished by its ability to dynamically route operand values directly from pipeline stages or reservation stations to functional units, thereby reducing data hazards and latency without waiting for register file updates.
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1.1K
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106
Authors
38
Institutions
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2017–2026
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Decoy Routing: Toward Unblockable Internet Communication
Josh Karlin, Daniel Ellard, Alden W. Jackson et al. · Foundations of Computational Intelligence · 2011 · 114 citations
Toward Ideal On-Chip Communication Using Express Virtual Channels
Amit Kumar, Li-Shiuan Peh, Partha Kundu et al. · IEEE Micro · 2008 · 94 citations
Hierarchical scheduling windows
Edward Brekelbaum, Jeff Rupley, Chris Wilkerson et al. · 2002 · 69 citations
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Princeton University
Princeton, United States
3 h-index
9 publications
534 citations
Intel (United States)
Santa Clara, United States
3 h-index
9 publications
510 citations
Northern Microdesign (United States)
Chapel Hill, United States
2 h-index
2 publications
31 citations
University of Wisconsin–Madison
Madison, United States
2 h-index
4 publications
118 citations
The University of Texas at Austin
Austin, United States
2 h-index
5 publications
80 citations
Texas A&M University
College Station, United States
1 h-index
4 publications
68 citations
Monarch Media (United States)
Santa Cruz, United States
1 h-index
1 publications
18 citations

Nara Institute of Science and Technology
Ikoma, Japan
1 h-index
6 publications
72 citations
1–8 of 38
1 publications · 11 citations
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1 publications · 22 citations
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1 publications · 21 citations
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Conference · 1 publications · 114 citations
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1 publications · 65 citations
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