Boolean Logic Optimization
Boolean Logic Optimization is a systematic method in digital integrated circuit design that reduces the complexity of Boolean expressions to minimize logic gates and improve circuit performance while preserving functional equivalence.
197
Publications
7.6K
Citations
416
Authors
187
Institutions
Publications per year
2017–2026
32
197
Targeting cells with single vectors using multiple-feature Boolean logic
Lief E. Fenno, Joanna Mattis, Charu Ramakrishnan et al. · Nature Methods · 2014 · 582 citations
1–5 of 197
416
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École Polytechnique Fédérale de Lausanne, Switzerland
7 publications · 390 citations
7
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6
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6
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6
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1–5 of 416
187
University of California, Berkeley
Berkeley, United States
11 h-index
22 publications
1.1K citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
8 h-index
23 publications
1.2K citations
University of California, Santa Barbara
Santa Barbara, United States
7 h-index
9 publications
478 citations
University of Southern California
Los Angeles, United States
6 h-index
12 publications
453 citations
Nanyang Technological University
Singapore, Singapore
6 h-index
11 publications
186 citations
Synopsys (United States)
Mountain View, United States
5 h-index
5 publications
130 citations
University of California, Los Angeles
Los Angeles, United States
5 h-index
8 publications
156 citations
University of Bremen
Bremen, Germany
5 h-index
12 publications
264 citations
1–8 of 187
12 publications · 702 citations
12
h-index
7 publications · 301 citations
7
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5 publications · 198 citations
5
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4 publications · 84 citations
4
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Conference · 3 publications · 100 citations
3
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1–5