Boolean Logic Optimization

Boolean Logic Optimization is a systematic method in digital integrated circuit design that reduces the complexity of Boolean expressions to minimize logic gates and improve circuit performance while preserving functional equivalence.

197

Publications

7.6K

Citations

416

Authors

187

Institutions

Publications per year

2017–2026

32

Authors

416

  1. RD
    Rolf Drechsler

    University of Bremen, Germany

    10 publications · 283 citations

    10

    h-index

  2. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    7 publications · 390 citations

    7

    h-index

  3. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    6 publications · 312 citations

    6

    h-index

  4. BB
    Bernd Becker

    University of Freiburg, Germany

    6 publications · 195 citations

    6

    h-index

  5. LA
    Luca Amarù

    École Polytechnique Fédérale de Lausanne, Switzerland

    6 publications · 600 citations

    6

    h-index

1–5 of 416

Venues

  1. 12

    h-index

  2. IEEE Transactions on Computers

    7 publications · 301 citations

    7

    h-index

  3. IEEE Transactions on Electronic Computers

    5 publications · 198 citations

    5

    h-index

  4. International Journal of Electronics

    4 publications · 84 citations

    4

    h-index

  5. International Conference on Computer Aided Design

    Conference · 3 publications · 100 citations

    3

    h-index

1–5