Concepedia

Back-annotated Delay

Back-Annotated Delay is a delay modeling construct that represents timing information derived from post-layout simulation or physical synthesis and subsequently integrated into the design’s higher-level representation to refine timing analysis accuracy.

7

Publications

109

Citations

26

Authors

10

Institutions

Publications per year

2017–2026

1

Variants

Back-annotated Delays

Parents

Publications

7

Time-Delay Optimization of RSFQ Cells

Samuel Intiso, Irina Kataeva, E. Tolkacheva et al. · IEEE Transactions on Applied Superconductivity · 2005 · 26 citations

, , +17

Timing optimization on routed designs with incremental placement and routing characterization

Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2000 · 23 citations

, , +17

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions

Jordi Cortadella, Michael Kishinevsky, Steven M. Burns et al. · RECERCAT (Consorci de Serveis Universitaris de Catalunya) · 1999 · 14 citations · Full text

, , +17

Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

Amol Inamdar, Jushya Ravi, Stephen Miller et al. · IEEE Transactions on Applied Superconductivity · 2021 · 14 citations

, , +15

Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets

Parisa Razaghi, Andreas Gerstlauer · IEEE Embedded Systems Letters · 2012 · 11 citations

, , +17

1–5 of 7

Authors

26

  1. PR
    Parisa Razaghi

    The University of Texas at Austin, United States

    2 publications · 21 citations

    2

    h-index

  2. AG
    Andreas Gerstlauer

    The University of Texas at Austin, United States

    2 publications · 21 citations

    2

    h-index

  3. MK
    Michael Kishinevsky

    Intel (United States), United States

    1 publications · 14 citations

    1

    h-index

  4. KS
    Ken Stevens

    Intel (United States), United States

    1 publications · 14 citations

    1

    h-index

  5. SP
    Sanghun Park

    Ulsan National Institute of Science and Technology, South Korea

    1 publications · 11 citations

    1

    h-index

1–5 of 26

Institutions

10

  1. The University of Texas at Austin

    Austin, United States

    2 h-index

    4 publications

    42 citations

  2. Intel (United States)

    Santa Clara, United States

    1 h-index

    3 publications

    42 citations

  3. Universitat Politècnica de Catalunya

    Barcelona, Spain

    1 h-index

    1 publications

    14 citations

  4. University of California, Riverside

    Riverside, United States

    1 h-index

    2 publications

    46 citations

  5. Chalmers University of Technology

    Gothenburg, Sweden

    1 h-index

    5 publications

    130 citations

  6. Lomonosov Moscow State University

    Moscow, Russia

    1 h-index

    1 publications

    26 citations

  7. Institute for Design Problems in Microelectronics

    Moscow, Russia

    1 h-index

    1 publications

    26 citations

  8. Hypres (United States)

    Elmsford, United States

    1 h-index

    6 publications

    84 citations

1–8 of 10

Venues

  1. 2

    h-index

  2. IEEE Embedded Systems Letters

    1 publications · 11 citations

    1

    h-index

  3. 1

    h-index

  4. RECERCAT (Consorci de Serveis Universitaris de Catalunya)

    Repository · 1 publications · 14 citations

    1

    h-index

1–4