Publication | Closed Access
Time-Delay Optimization of RSFQ Cells
26
Citations
10
References
2005
Year
Mathematical ProgrammingVhdl DesignElectrical EngineeringTime Delay SystemEngineeringVlsi DesignHardware-in-the-loop SimulationUltra-low LatencyTiming AnalysisComputer EngineeringComputer ArchitectureHardware Description LanguageModeling And SimulationTimed SystemTime-delay OptimizationRsfq CellsSignal ProcessingVhdl Simulation
This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.
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