Asynchronous Logic Support
Asynchronous Logic Support is a configurable logic block feature that enables the implementation of sequential circuits without reliance on a global clock signal, distinguishing itself by facilitating event-driven state transitions through direct handshaking protocols between components.
15
Publications
486
Citations
35
Authors
22
Institutions
Publications per year
2017–2026
0
Parents
15
On processor coordination using asynchronous hardware
Benny Chor, Amos Israeli, Ming Li · 1987 · 117 citations · Full text
FPGA Architecture for Multi-Style Asynchronous Logic
N. Huot, H. Dubreuil, Laurent Fesquet et al. · Design, Automation, and Test in Europe · 2005 · 37 citations · Full text
1–5 of 15
35
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Pontifícia Universidade Católica do Rio Grande do Sul, Brazil
2 publications · 27 citations
2
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2
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Pontifícia Universidade Católica do Rio Grande do Sul, Brazil
2 publications · 27 citations
2
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1–5 of 35
22
Columbia University
New York, United States
2 h-index
2 publications
47 citations

Pontifícia Universidade Católica do Rio Grande do Sul
Porto Alegre, Brazil
2 h-index
8 publications
108 citations
Hewlett-Packard (United States)
Palo Alto, United States
1 h-index
3 publications
150 citations
Space (Italy)
Prato, Italy
1 h-index
2 publications
24 citations
University of California, Berkeley
Berkeley, United States
1 h-index
1 publications
28 citations
Harvard University
Cambridge, United States
1 h-index
3 publications
351 citations
California Institute of Technology
Pasadena, United States
1 h-index
1 publications
122 citations
Center for Sustainable Future Technologies
Turin, Italy
1 h-index
2 publications
24 citations
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Conference · 1 publications · 37 citations
1
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1 publications · 12 citations
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1 publications · 50 citations
1
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1 publications · 122 citations
1
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1 publications · 11 citations
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