Arithmetic Logic Optimization
Arithmetic Logic Optimization is a computational methodology within digital signal processing that systematically minimizes the arithmetic and logical operations in signal processing algorithms to enhance computational efficiency and reduce hardware resource utilization.
64
Publications
3K
Citations
157
Authors
84
Institutions
Publications per year
2017–2026
14
64
1–5 of 64
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84
University of California, Los Angeles
Los Angeles, United States
3 h-index
6 publications
138 citations
University of Kassel
Kassel, Germany
3 h-index
7 publications
158 citations

Indian Institute of Technology Bombay
Mumbai, India
2 h-index
4 publications
260 citations
Nanyang Technological University
Singapore, Singapore
2 h-index
6 publications
246 citations
University of California, Irvine
Irvine, United States
2 h-index
2 publications
20 citations
Massachusetts Institute of Technology
Cambridge, United States
2 h-index
4 publications
200 citations
Shahid Beheshti University
Tehran, Iran
2 h-index
4 publications
122 citations

Linköping University
Linköping, Sweden
2 h-index
4 publications
98 citations
1–8 of 84
3 publications · 463 citations
3
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2 publications · 100 citations
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2 publications · 92 citations
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Repository · 1 publications · 290 citations
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1 publications · 33 citations
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1–5