Address Decoding

Address Decoding is a hardware-level mechanism in Memory-Mapped I/O systems that selects a specific peripheral device or register by interpreting the address lines of the processor bus to map physical memory addresses to corresponding I/O device locations.

18

Publications

585

Citations

70

Authors

25

Institutions

Publications per year

2017–2026

2

Authors

70

  1. MB
    Manoj Bidnurkar

    New York University, United States

    1 publications · 41 citations

    1

    h-index

  2. LY
    Lei Yu

    Wuhan University, China

    1 publications · 16 citations

    1

    h-index

  3. LY
    Leonid Yavits

    Technion – Israel Institute of Technology, Israel

    1 publications · 10 citations

    1

    h-index

  4. TY
    T. Yamazaki

    NEC (Japan), Japan

    1 publications · 16 citations

    1

    h-index

  5. MS
    Majd Sakr

    Carnegie Mellon University, United States

    1 publications · 41 citations

    1

    h-index

1–5 of 70

Venues

  1. Journal of Electronic Testing

    JETTA · 1 publications · 14 citations

    1

    h-index

  2. 1

    h-index

  3. Health & Place

    1 publications · 70 citations

    1

    h-index

  4. IEEE Computer Architecture Letters

    1 publications · 10 citations

    1

    h-index

  5. 1

    h-index

1–5