This article introduces a high fill factor (FF) and low dark count rate (DCR) back-illuminated single photon avalanche diode (SPAD) pixel array fabricated in customized 55nm CMOS technology. In the SPAD array, all pixels use the same deep N-well (DNW) and adjacent pixels share the same N ⁺ and N-well. The fill factor reaches 41.6%. Furthermore, deep trench isolation (DTI) is used to reduce optical crosstalk. For a single SPAD design, the shallow trench isolation (STI) is isolated away from avalanche multiplication zone to reduce the DCR. The array contains of

${8}\,\,\times \,\,{8\,4}\,\,\mu \text{m}$

pixels whose active area diameter is

$2.6~\mu \text{m}$

. At room temperature, the DCR of the SPAD is only 0.03Hz

$/ \mu \text{m}^{{2}}$

at 1.0 V excess bias and 0.36Hz

$/ \mu \text{m}^{{2}}$

at 2.5 V excess bias. The full width at half maximum (FWHM) jitter at 640nm wavelength is 180 ps and the photon detection efficiency (PDE) at 905nm wavelength is 5%. The SPAD array shows excellent performance for time-of-flight (ToF) applications.

Wenbo Sun

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