Yoshinori Kohama - Concepedia

Author

Yoshinori Kohama

Keio University

Also Known As

Yoshinori Kohama

Publications

286

Citations

H-Index

Concepts

All Affiliations

Keio University Hitachi (Japan)The University of Tokyo Renesas Electronics (United States)

About

Yoshinori Kohama is an author at Keio University specializing in engineering, microelectronics, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	278
2	Computer Engineering	9	9	278
3	Electrical Engineering	8	8	261
4	Computer Architecture	6	6	218
5	Integrated Circuits	2	2	47

Yoshinori Kohama

Publications

278

Citations

H-Index

Page 1

	Year	Citations
An 11Gb/s Inductive-Coupling Link with Burst Transmission Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, PhotonicsElectrical EngineeringEngineeringVlsi DesignInductive-coupling Link	2008	74
A High-Speed Inductive-Coupling Link With Burst Transmission Noriyuki Miura, Yoshinori Kohama, Yasfumi Sugimori, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignHigh-frequency DeviceNm Cmos	2009	61
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link Makoto Saen, Kenichi Osada, Yasuyuki Okuma, IEEE Journal of Solid-State Circuits Inductive CouplingEngineeringVlsi DesignMemory ChipsDevice Integration	2010	31
Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Electrical EngineeringEngineeringVlsi DesignPower/signal LinesInductive-coupling Link	2007	31
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, IEEE Journal of Solid-State Circuits Hardware SecurityGb/s 15Electrical EngineeringSolid State DriveEngineering	2010	19
A scalable 3D processor by homogeneous chip stacking with inductive-coupling link Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, EngineeringVertical LinkHomogeneous ChipComputer ArchitectureProcessor Architecture	2009	17
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3D Ic ArchitectureElectrical EngineeringInductive-coupling Inter-chip LinkEngineeringExperimental Verification	2009	17
3D system integration of processor and multi-stacked SRAMs by using inductive-coupling links Kenichi Osada, Makoto Saen, Yasuyuki Okuma, Inductive CouplingEngineeringVlsi DesignMemory ChipsDevice Integration	2009	16
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Electrical EngineeringInductive-coupling Inter-chip LinkEngineeringVlsi DesignCircuit System	2010	12

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