Shih‐Lien L. Lu - Concepedia

Author

Shih‐Lien L. Lu

Intel (United States)

Also Known As

Shih-Lien L Lu, Shih-Lien L. Lu, Shih‐Lien L. Lu

Publications

903

Citations

H-Index

Concepts

All Affiliations

Intel (United States)Carnegie Mellon University Intel (United Kingdom)

About

Shih‐Lien L. Lu is an author at Intel (United States) specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	825
2	Computer Engineering	9	9	825
3	Computer Science	6	6	428
4	Education	1	1	36
5	Medicine	1	1	337

Shih‐Lien L. Lu

Publications

852

Citations

H-Index

Page 1

	Year	Citations
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance Keith Bowman, James Tschanz, Nam Sung Kim, IEEE Journal of Solid-State Circuits Equal ThroughputEngineeringVlsi DesignDatapath MetastabilityArtificial Immune System	2009	337
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance Keith Bowman, James Tschanz, Shih‐Lien L. Lu, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignMicroprocessor CoreComputer ArchitectureIntegrated Circuits	2010	259
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance Keith Bowman, James Tschanz, Nam Sung Kim, EngineeringVlsi DesignAnalog DesignMicroprocessor Clock FrequencyComputer Architecture	2008	84
An FPGA-based Pentium® in a complete desktop system Shih‐Lien L. Lu, Peter Yiannacouras, Rolf Kassa, Hardware ModelingEmulation TechniqueEngineeringHardware AlgorithmComputer Architecture	2007	38
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control Keith Bowman, Carlos Tokunaga, James Tschanz, IEEE Transactions on Circuits and Systems I Regular Papers EngineeringVlsi DesignMeasurementComputer ArchitectureEducation	2011	36
Automatic Pipelining From Transactional Datapath Specifications Eriko Nurvitadhi, Timothy Kam, Shih‐Lien L. Lu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	2011	27
Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance Keith Bowman, James Tschanz, Nam Sung Kim, Equal ThroughputEngineeringIntegrated CircuitsDynamic Variation ToleranceHardware Systems	2008	24
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays Arijit Raychowdhury, Bibiche Geuskens, Keith Bowman, IEEE Journal of Solid-State Circuits Hardware SecurityNon-volatile MemoryEngineeringVlsi DesignPhysics	2011	21
Automatic multithreaded pipeline synthesis from transactional datapath specifications Eriko Nurvitadhi, James C. Hoe, Shih‐Lien L. Lu, Sequential DatapathEngineeringMultithreaded In-order PipelineComputer ArchitectureSoftware Engineering	2010	14
Design, implementation, and verification of active cache emulator (ACE) Jumnit Hong, Eriko Nurvitadhi, Shih‐Lien L. Lu Emulation TechniqueEngineeringComputer ArchitectureProcessor ArchitectureFormal Verification	2006	12

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