Shianling Wu

VirtualScan: a new compressed scan technology for test cost reduction

L.-T. Wang, Xiaoqing Wen, Hiroshi Furukawa et al. · 2005 · 104 citations

Engineering, Computer Architecture, Virtual Instrumentation +18

A Sequential Circuit Test Generation System.

Sivanarayana Mallela, Shianling Wu · International Test Conference · 1985 · 80 citations

Engineering, Program Analysis, Software Testing +7

Built-in Self-Test for Digital Integrated Circuits

Vishwani D. Agrawal, Chih‐Jen Lin, Paul W. Rutkowski et al. · AT&T Technical Journal · 1994 · 59 citations

Hardware Security, Ic Testing, Engineering +13

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

Laung‐Terng Wang, Xiaoqing Wen, Shianling Wu et al. · IEEE Design & Test of Computers · 2008 · 39 citations

Engineering, Mem Testing, Computer Architecture +21

At-speed logic BIST architecture for multi-clock designs

L. Wang, Xiaoqing Wen, Po‐Ching Hsu et al. · 2006 · 23 citations

Electrical Engineering, Engineering, Vlsi Design +13