Shunsuke Okumura - Concepedia

Author

Shunsuke Okumura

Kobe University

Also Known As

Shunsuke OKUMURA, Shunsuke Okumura

Publications

325

Citations

H-Index

Concepts

All Affiliations

Kobe University Renesas Electronics (Japan)Japan Science and Technology Agency

About

Shunsuke Okumura is an author at Kobe University specializing in computer engineering, computer architecture, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	11	253
2	Computer Engineering	11	11	253
3	Electrical Engineering	8	8	203
4	Computer Science	5	5	85
5	Physics	1	1	11

Shunsuke Okumura

Publications

263

Citations

H-Index

Page 1

	Year	Citations
Which is the best dual-port SRAM in 45-nm process technology? &#x2014; 8T, 10T single end, and 10T differential &#x2014; Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignProposed Sram	2008	77
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Low-power ElectronicsNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design	2009	28
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design	2009	22
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm<sup>2</sup> Shunsuke Okumura, Makoto Yabuuchi, K. Hijioka, Convolutional Neural NetworkEngineeringHardware AccelerationMany-core Processing-in-memory ArchitectureTernary Sram	2019	22
Quality of a Bit (QoB): A New Concept in Dependable SRAM Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hardware SecurityNon-volatile MemoryElectrical EngineeringTypical ModeEngineering	2008	20
7T SRAM enabling low-energy simultaneous block copy Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Hardware SecurityEnergy ConsumptionCheckpoint Data StorageNon-volatile MemoryEngineering	2010	16
A Dependable SRAM with 7T/14T Memory Cells Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, IEICE Transactions on Electronics Electrical EngineeringMemory ArchitectureEngineeringMemory DesignDependable Sram	2009	15
NMOS-inside 6T SRAM layout reducing neutron-induced multiple cell upsets Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Non-volatile MemoryElectrical EngineeringHorizontal Mcu SerEngineeringNanoelectronics	2012	15
Bit error rate estimation in SRAM considering temperature fluctuation Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Hardware SecurityElectrical EngineeringEngineeringVlsi DesignStatic Noise Margin	2012	15
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm<sup>2</sup> Shunsuke Okumura, Makoto Yabuuchi, K. Hijioka, Convolutional Neural NetworkEngineeringHardware AccelerationMany-core Processing-in-memory ArchitectureTernary Sram	2019	12

Page 1