A Flexible Framework for the Automatic Generation of SBST Programs

Andreas Riefert, Riccardo Cantoro, Matthias Sauer, +2

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Software MaintenanceEngineeringVerificationComputer ArchitectureTest Data Generation +24

Small-delay-fault ATPG with waveform accuracy

Matthias Sauer, Alexander Czutro, Ilia Polian, +1

EngineeringVerificationSoftware AnalysisFormal VerificationHardware Security +19

Exploring the Mysteries of System-Level Test

Ilia Polian, Jens Anders, Steffen Becker, +7

Software MaintenanceEngineeringVerificationSoftware EngineeringSystem-level Design +18

Equivalence checking of partial designs using dependency quantified Boolean formulae

Karina Gitina, Sven Reimer, Matthias Sauer, +3

Circuit ComplexityLogic SynthesisQbf ApproximationsEngineeringBoolean Function +13

Functional test of small-delay faults using SAT and Craig interpolation

Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, +3

EngineeringVerificationComputer ArchitectureFormal VerificationHardware Security +21

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects

Dominik Erb, Karsten Scheibler, Matthias Sauer, +2

Device ModelingElectrical EngineeringEngineeringVlsi DesignNanotechnology +11

Towards the formal verification of security properties of a Network-on-Chip router

Johanna Sepúlveda, Damian Aboul--Hassan, Georg Sigl, +2

EngineeringInformation SecurityVerificationNetwork-on-chip RouterComputer-aided Verification +20

Efficient SAT-Based Search for Longest Sensitisable Paths

Matthias Sauer, Jie Jiang, Alexander Czutro, +2

Circuit ComplexityEngineeringVersatile MethodVerificationComputational Complexity +16

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions

Thomas Lueftner, Joerg Berthold, C. Pacha, +16

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringGsm/edge Baseband ProcessorArm926 CoreVlsi Design +13

Solving DQBF Through Quantifier Elimination

Karina Gitina, Ralf Wimmer, Sven Reimer, +3

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015

Circuit ComplexityStandard Qbf SolverEngineeringBoolean FunctionVerification +15