Toshihisa Nonaka - Concepedia

Author

Toshihisa Nonaka

Toray Industries, Inc. (Japan)

Also Known As

Toshihisa NONAKA, Toshihisa Nonaka

Publications

527

Citations

H-Index

Concepts

All Affiliations

Toray Industries, Inc. (Japan)Toray (United States)Waseda University Hitachi (Japan)

About

Toshihisa Nonaka is an author at Toray Industries, Inc. (Japan) specializing in engineering, materials science, and electronic packaging.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	454
2	Materials Science	8	8	156
3	Applied Physics	7	7	394
4	Materials Engineering	5	5	120
5	Mechanical Engineering	4	4	73

Toshihisa Nonaka

Publications

454

Citations

H-Index

Page 1

	Year	Citations
Crystal structure of GeTe and Ge2Sb2Te5 meta-stable phase Toshihisa Nonaka, Gentaro Ohbayashi, Yoshiharu Toriumi, Thin Solid Films Crystal StructureEngineeringCrystal MaterialApplied PhysicsCondensed Matter Physics	2000	298
High throughput thermal compression NCF bonding Toshihisa Nonaka, Y. Kobayashi, Noboru Asahi, EngineeringMechanical EngineeringAssembled Test VehicleTest VehicleStructural Materials	2014	37
Ba-Y-Cu-O Thin Films Fabricated by Dip Coating Using Concentrated Mixed Alkoxide Solution Toshihisa Nonaka, Kimiyoshi Kaneko, Tetsuya Hasegawa, Japanese Journal of Applied Physics Materials ScienceMaterials EngineeringSuperconducting MaterialHigh-tc SuperconductivityEngineering	1988	32
Warpage Suppression during FO-WLP Fabrication Process Masaaki Takekoshi, Keisuke Nishido, Yuhei Okada, Materials EngineeringMaterials ScienceAdvanced PackagingMaterial CombinationEngineering	2017	23
Development of wafer level NCF (non conductive film) Toshihisa Nonaka, Koichi Fujimsru, Noboru Asahi, Materials EngineeringMaterials ScienceWafer Scale ProcessingConductive FilmEngineering	2008	15
Low temperature touch down and suppressing filler trapping bonding process with a wafer level pre-applied underfilling film adhesive Toshihisa Nonaka, Shoichi Niizeki, Noboru Asahi, EngineeringIntegrated CircuitsLow TemperatureFlip ChipWafer Scale Processing	2012	13
Compensation of Surface Roughness Using an Au Intermediate Layer in a Cu Direct Bonding Process Hirokazu Noma, Takumi Kamibayashi, Hiroyuki Kuwae, Journal of Electronic Materials Materials EngineeringMaterials ScienceSurface CharacterizationEngineeringSurface Roughness	2018	13
Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection Masaki Ohyama, Masatsugu Nimura, Jun Mizuno, Microelectronics Reliability Materials Science3D Ic ArchitectureWafer Scale ProcessingSingle-micron PitchEngineering	2016	12
Wafer and/or chip bonding adhesives for 3D package Toshihisa Nonaka, Koichi Fujimaru, Akira Shimada, Materials ScienceAdvanced PackagingBump Top AdhesivePackage ApplicationEngineering	2010	11

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