B. Hoppe

Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

B. Hoppe, G. Neuendorf, D. Schmitt‐Landsiedel et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990 · 79 citations

Engineering, Computer Engineering, Electrical Engineering +17

A hardware implementation of a run length encoding compression algorithm with parallel inputs

Josef Philipp Trein, Andreas Schwarzbacher, B. Hoppe et al. · 2008 · 18 citations

Computing, Computer Engineering, Computer Science +17

Pipelined architecture for fast CMOS buffer RAMs

D. Schmitt‐Landsiedel, B. Hoppe, G. Neuendorf et al. · IEEE Journal of Solid-State Circuits · 1990 · 15 citations

Engineering, Computer Engineering, Electrical Engineering +16