Yuji Kihara

A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue

Yukiko Ishii, Hiroshi Fujiwara, Koji Nii et al. · 2010 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka et al. · IEEE Journal of Solid-State Circuits · 2011 · 26 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto et al. · 2010 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

Yukiko Ishii, Hiroshi Fujiwara, Shinji Tanaka et al. · 2010 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +15

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

Yasumasa Tsukamoto, Takuya Kida, T. Yamaki et al. · 2011 · 11 citations

Engineering, Computer Engineering, Computer Science +9