A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue

Abstract

We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vdd <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ). Active bitline equalizing technique improves the write margin whenever a write-disturb occurs. This technique is applicable for both synchronous and asynchronous clock frequencies between ports. We designed and fabricated a 256 kb DP-SRAM macro using 28-nm low-power CMOS technology and achieved low-voltage operation at 0.66 V and 1.4 ns write access time at 25°C, which are 120 mV lower and 40% faster than the conventional performance.