Ashish Pal

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Ashish Pal, Angada B. Sachid, V. Ramgopal Rao · IEEE Transactions on Electron Devices · 2011 · 124 citations

Device Modeling, Low-power Electronics, Electrical Engineering +15

Materials to Systems Co-Optimization Platform for Rapid Technology Development Targeting Future Generation CMOS Nodes

El Mehdi Bazizi, Ashish Pal, Jongchol Kim et al. · IEEE Transactions on Electron Devices · 2021 · 29 citations

Traditional Dtco, Engineering, Co-optimization Platform +18

Complementary FET Device and Circuit Level Evaluation Using Fin-Based and Sheet-Based Configurations Targeting 3nm Node and Beyond

Jiang Liu, Ashish Pal, El Mehdi Bazizi et al. · 2020 · 13 citations

Engineering, Vlsi Design, Interconnect (Integrated Circuits) +16

Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node

Ashish Pal, Sanjay Natarajan, Buvna Ayyagari et al. · 2019 · 11 citations

Technology Node, Electrical Engineering, Engineering +13

Next Generation Gate-all-around Device Design for Continued Scaling Beyond 2 nm Logic

Pratik B. Vyas, Charisse Zhao, S. Dağ et al. · 2023 · 10 citations