Jize Jiang

A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point

Jize Jiang, Wei Shu, Joseph S. Chang · IEEE Journal of Solid-State Circuits · 2016 · 101 citations

Low-power Electronics, Electrical Engineering, Engineering +7

A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

Jize Jiang, Wei Shu, Joseph S. Chang · IEEE Journal of Solid-State Circuits · 2018 · 92 citations

Low-power Electronics, 10-Mhz Frequency Range, Engineering +6

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

D. Zhang, Bich-Yen Nguyen, T. White et al. · 2005 · 24 citations

Electrical Engineering, Sige S/d Pmos, Engineering +12

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process

Jize Jiang, Wei Shu, Kwen‐Siong Chong et al. · 2016 · 11 citations · Full text

Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process

Tong Lin, Kwen‐Siong Chong, Wei Shu et al. · 2016 · 11 citations

Engineering, Vlsi Design, Radiation-hardened Flip-flops +18