Fahim ur Rahman

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

Venkata Rajesh Pamula, Xun Sun, Sung Hoon Kim et al. · 2018 · 34 citations

Engineering, Vlsi Design, Analog Design +16

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Fahim ur Rahman, Sung Kim, Naveen John et al. · IEEE Journal of Solid-State Circuits · 2019 · 31 citations

Processor Energy Efficiency, Vlsi Design, Engineering +20

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

Fahim ur Rahman, G. Taylor, Visvesh Sathe · IEEE Journal of Solid-State Circuits · 2019 · 31 citations

A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction

Venkata Rajesh Pamula, Xun Sun, Sung Kim et al. · IEEE Solid-State Circuits Letters · 2018 · 22 citations

Engineering, Pseudo-random Sequence, Integrated De-correlation +16

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

Xun Sun, Sung Kim, Fahim ur Rahman et al. · 2018 · 15 citations

Low-power Electronics, Ivr Implementations, Electrical Engineering +14