Detachment and transfer of ordered TiO2 nanotube arrays for front-illuminated dye-sensitized solar cells

Lulin Li, Yi‐Ju Chen, Huiping Wu, +2

Energy & Environmental Science

Materials ScienceChemical EngineeringEngineeringNanoengineeringNanomaterials +11

FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

Angada B. Sachid, Yao-Min Huang, Yi‐Ju Chen, +4

IEEE Electron Device Letters

Low-power ElectronicsAir-spacer FinfetElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors) +9

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, +3

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringTernary Content-addressable MemoryEngineeringVlsi Design +9

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

Meng‐Fan Chang, Chien-Fu Chen, Ting-Hao Chang, +4

IEEE Journal of Solid-State Circuits

Electrical EngineeringCvss VoltageEngineeringVlsi DesignEmerging Memory Technology +11

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Yao‐Jen Lee, Ta-Chun Cho, Po-Jung Sung, +25

EngineeringMicrowave AnnealingOptoelectronic DevicesIntegrated CircuitsSilicon On Insulator +17

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Kai‐Shin Li, Yun-Jie Wei, Yi‐Ju Chen, +13

EngineeringInf XmlnsPower ElectronicsMagnetismNanoelectronics +14

Improved Electrical Characteristics of Bulk FinFETs With SiGe Super-Lattice-Like Buried Channel

Yanlin Li, Kuei‐Shu Chang‐Liao, Chen-Chien Li, +7

IEEE Electron Device Letters

Electrical CharacteristicsElectrical EngineeringEngineeringRf SemiconductorNanoelectronics +10

MoS<inf>2</inf> U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS<inf>2</inf> availability

Kai‐Shin Li, Bowei Wu, Lain‐Jong Li, +13

EngineeringNm Channel LengthChemical DepositionChannel RegionSemiconductor Device +15

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network

Xiaoyu Sun, Rui Liu, Yi‐Ju Chen, +4

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

EngineeringEmerging Memory TechnologyComputer ArchitectureLow-vdd OperationEdge Devices +17

Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing

Chunmeng Dou, Wei-Hao Chen, Yi‐Ju Chen, +4

Artificial IntelligenceNon-volatile MemoryEngineeringEmerging Memory TechnologyComputer Architecture +18