Pouria Bastani - Concepedia

Author

Pouria Bastani

University of California, Santa Barbara

Also Known As

Bastani, P., P. Bastani, Pouria Bastani

Publications

263

Citations

H-Index

Concepts

All Affiliations

University of California, Santa Barbara Intel (United States)

About

Pouria Bastani is an author at University of California, Santa Barbara specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	226
2	Management	2	2	28
3	Education	1	1	38
4	Public Health	1	1	21
5	Biostatistics	1	1	21

Pouria Bastani

Publications

239

Citations

H-Index

Page 1

	Year	Citations
Speedpath prediction based on learning from a small set of examples Pouria Bastani, Kip Killpack, Li-C. Wang, Traffic TheoryEngineeringVlsi DesignMachine LearningSmall Set	2008	53
Design-silicon timing correlation Li-C. Wang, Pouria Bastani, Magdy S. Abadir Proceedings - ACM IEEE Design Automation Conference Physical Design (Electronics)Delay Test DataEngineeringMeasurementDesign-silicon Timing Correlation	2007	38
Case Study on Speed Failure Causes in a Microprocessor Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, IEEE Design & Test of Computers EngineeringVlsi DesignComputer ArchitecturePerformance IssueHardware Security	2008	35
Analyzing the risk of timing modeling based on path delay tests. Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Hardware ModelingTechnology ScalesEngineeringReal-time System DesignComputer Architecture	2007	22
Statistical diagnosis of unmodeled systematic timing effects Pouria Bastani, Nicholas Callegari, Li-C. Wang, Fault DiagnosisEngineeringMachine LearningObserved Timing BehaviorDiagnosis	2008	21
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained Pouria Bastani, Nick Callegari, Li-C. Wang, EngineeringMachine LearningElectronic Design AutomationComputer ArchitectureSub-65 Nm Design	2008	18
Path selection for monitoring unexpected systematic timing effects Nicholas Callegari, Pouria Bastani, Li-C. Wang, Asia and South Pacific Design Automation Conference EngineeringIndustrial EngineeringPath ClusteringComputer ArchitecturePath Encoding	2009	14
Path selection for monitoring unexpected systematic timing effects Nicholas Callegari, Pouria Bastani, Li-C. Wang, EngineeringIndustrial EngineeringPath ClusteringComputer ArchitecturePath Encoding	2009	14
Design-Silicon Timing Correlation A Data Mining Perspective Li-C. Wang, Pouria Bastani, Magdy S. Abadir Proceedings - ACM IEEE Design Automation Conference	2007	13
Speedpath analysis based on hypothesis pruning and ranking Nicholas Callegari, Li-C. Wang, Pouria Bastani Transport Network AnalysisEngineeringVlsi DesignTraffic FlowComputer Architecture	2009	11

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