Jorge Lagos - Concepedia

Author

Jorge Lagos

IMEC ORCID

Also Known As

J. L. Lagos, J. Lagos, J. Lagos-Benites, Jorge L. Lagos, Jorge Lagos

Publications

624

Citations

H-Index

Concepts

All Affiliations

IMEC University of Macau Polytechnic University of Turin Institute of Microelectronics

About

Jorge Lagos is an author at IMEC specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	11	11	401
2	Engineering	9	9	309
3	Electrical Engineering	3	3	130
4	Computer Science	1	1	25
5	Systems Engineering	1	1	25

Jorge Lagos

Publications

560

Citations

H-Index

Page 1

	Year	Citations
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers Jorge Lagos, Benjamin Hershberg, Ewout Martens, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringData ConverterMixed-signal Integrated CircuitRing Amplifier	2019	75
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS Jorge Lagos, Benjamin Hershberg, Ewout Martens, IEEE Journal of Solid-State Circuits Data ConverterMixed-signal Integrated CircuitRing AmplifierAnalog Design28-Nm Cmos	2018	69
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS Jorge Lagos, Nereo Markulić, Benjamin Hershberg, IEEE Journal of Solid-State Circuits EngineeringCalibrationData ConverterAnalog DesignBias Optimality	2022	51
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion Benjamin Hershberg, Davide Dermit, Barend van Liempd, IEEE Journal of Solid-State Circuits	2021	46
3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion Benjamin Hershberg, Davide Dermit, Barend van Liempd, Background MonitoringEnob 61MwEngineeringResidue AmplificationData Converter	2019	41
Worst-Case Induced Disturbances in Digital and Analog Interchip Interconnects by an External Electromagnetic Plane Wave—Part I: Modeling and Algorithm Jorge Lagos, Franco Fiori IEEE Transactions on Electromagnetic Compatibility EngineeringEm Plane WaveAnalog DesignIntegrated CircuitsInterconnect (Integrated Circuits)	2010	37
A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS Jorge Lagos, Benjamin Hershberg, Ewout Martens, Pipelined AdcData ConverterMixed-signal Integrated CircuitRing AmplifierCmos Resistors	2017	28
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Zihao Zheng, Lai Wei, Jorge Lagos, EngineeringResidue AmplificationPost-amplification Residue GenerationCalibration ComplexitySingle-channel 5.5Mw	2020	28
On-line software-based self-test of the Address Calculation Unit in RISC processors Paolo Bernardi, L. Ciganda, Maurício Carvalho, EngineeringHardware Verification LanguageMeasurementMem TestingHardware Integrity	2012	25
3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm Benjamin Hershberg, Barend van Liempd, Nereo Markulić,	2019	25

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